Due to the progress of miniaturization of semiconductors, it is anticipated that temporary faults such as software errors will frequently occur.
FIG. 1 diametrically illustrates an example of the configuration of a temporary-fault tolerant device in which measures have been taken against temporary faults using circuits. The example shown in FIG. 1 has a configuration wherein a flip-flop circuit within CPU 11 is replaced with temporary-fault tolerant flip-flop circuit 200. Temporary-fault tolerant flip-flop circuit 200 has a circuit design that prevents the occurrence of temporary faults. Thus, CPU 11 can take measures against temporary faults on a circuit basis.
However, the system shown in FIG. 1 presents the problem that since the area of the temporary-fault tolerant flip-flop circuit is very large as compared with the area of a conventional flip-flop circuit, the area of CPU 11 will be remarkably increased.
As a technique to address this problem, Patent literature 1 discloses a flip-flop circuit that is constructed from a bipolar-type semiconductor. Specifically, Patent literature 1 discloses a circuit wherein a software error protection resistor is inserted within the flip-flop circuit constructed from a bipolar-type semiconductor. Consequently, Patent literature 1 suffers from the same problem as in the system shown in FIG. 1.
FIG. 2 illustrates an exemplary configuration to cope with temporary faults by making use of plural processing. In the example shown in FIG. 2, precedent thread 13 and succeeding thread 14 are generated and the results of execution of the threads are compared with each other in thread-parallel type CPU 12 for the detection of temporary faults. By again executing the threads, the example shown in FIG. 2 copes with temporary faults. Thus, temporary faults can be coped with, without increasing the circuit area so much.
However, the system shown in FIG. 2 necessitates use of the thread-parallel type CPU, and utilizes the thread-parallel processing to detect temporary faults. As a result, the system is unable to realize the original performance that the CPU delivers. Further, since plural threads are executed, the amount of usage of the memory is increased.
As a technique to address this problem, Patent literature 2 discloses a CPU technique to support the execution of the plural threads. Consequently, Patent literature 2 suffers from the same problem as in the system shown in FIG. 2.
Patent literature 1: JPH6-350037A
Patent literature 2: JP2005-149496A